Switching Mechanisms

Content Addressable Memory, High-speed memory, single CPU cycle

Get value back based on the exact content.

MAC Addresses, Interfaces, VLAN IDs

Updated as traffic flows through the switch

Ternary Content Addressable Memory, High-speed memory, single CPU cycle, limited amount

Match on 0,1,X

value, mask, result (allow/deny, next hop)

IP Routing, ACL, QOS

IPv6 takes 2 x memory space

RIB stands for Routing Information Base (Routing Table), and it is a bit like a repository where all routing protocols store IP routing information. It includes dynamically and statically learned routes and directly connected route information.

Administrative Distance, longest prefix match, metric

Network ID, Mask, how learned about, AD, next hop (IP, Interface)

Rewrite L2 headers

store packet in memory

CPU runs ip_input (RIB lookup, next hop, ARP table)

CPU switches traffic

Uses process switching if not in cache

To enable on interface: ip route-cache

proactive cache, enabled by default

FIB stand for Forwarding Information Base and it contains information such as interface identifier and information how to reach the next hop network prefix. basically, it is used to make IP destination prefix based switching decision. The FIB mirror much the RIB, however the concept enable to separate the forwarding plane function of the forwarding table from the control plane function of the routing table, therefore each function does not impact on the performance of the other.

Adds MAC to next hop, recursive lookups to directly connected next hop

Centralised - CAB and FIB on supervisor (Used at edge)

Distributed - CAB and FIB pushed to line cards from supervisor (Used and core)